1) Field of the Invention
The present invention relates to an apparatus for information processing having a processor and a method of information processing.
2) Description of the Related Art
As the technology of semiconductor fine pattern processing advances, since each component in a circuit becomes smaller, the circuits mounted on Large Scale Integrated (LSI) chips became larger in scale. Moreover, development of a system (that is, a system LSI) in which a processor (that is, a central processing unit (CPU)) and custom made circuits are mounted on a chip has been conventionally carried out.
There are two types of methods for developing a system LSI suitable for a user's application: (1) a method of mounting circuit blocks according to the application independent of the processor, and (2) a method of correcting the processor itself according to the application.
The above (1) is a developing method to realize general system LSIs on a chip. The above (2) is a method of developing a configurable processor and is employed in Tensilca Inc. and ARC International. According to this method (2), an exclusive instruction suitable for a user's application (that is, a custom instruction) is added to the instruction set, and at the same time, a functional unit that executes the instruction is added to the processor.
However, as the processes become finer, the processing cost including the cost of masks increases considerably. Only some of the system LSIs, that is, the system LSIs that are produced in a very large quantity, are profitable, while most of the others are not. In other words, the above methods (1) and (2) are suitable for a mass production of the system LSIs and do not suit for manufacturing of the system LSIs in a small quantity.
On the other hand, in recent years, a mixed mounting of a processor and a Field Programmable Gate Array (FPGA) on a chip has been employed as a method (3), and products are actually available based on this method. According to this method, it is possible to realize various kinds of circuits corresponding to the user's applications, by using FPGA blocks. However, the area efficiency of the FPGA is as low as one-tenth to one-twentieth of that of the normal circuit, and therefore, the FPGA blocks are expensive. Further, it is not possible to obtain high operating frequency in the FPGA portion, and in order to obtain high performance, it is necessary to set these portions in a parallel layout. This results in the increase in the circuit scale.